Microarchitecture and Design Engineer - AI SoC

Location: On-site in Santa Clara or Folsom, California, United States

Annual salary: $164,470–$311,890 USD

Company

hirify.global designs and manufactures silicon products, including AI hardware for edge devices and data center accelerators.

What you will do

• Develop logic designs, RTL code, and simulations for SoC products.
• Define and implement architecture and microarchitecture features for logic blocks.
• Optimize RTL for power, performance, area, and timing targets.
• Perform RTL, timing, power, and design-integrity quality checks.
• Collaborate with IP providers to integrate and validate IP at the SoC level.
• Review verification plans, resolve RTL test failures, and support secure IP and SoC handoff.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 5–9+ years of experience depending on degree level: 9+ years with a Bachelor's, 6+ with a Master's, or 5+ with a PhD.
• Expertise in microarchitecture, RTL design, coding, and simulation using SystemVerilog.
• Strong knowledge of system-level design, including power, performance, and area optimization.
• Experience with timing and power convergence methodologies and tools.
• On-site presence in Santa Clara or Folsom, California is required.

Nice to have

• Experience with SoC architecture and SoC microarchitecture.
• Proficiency in clock domain crossing analysis and implementation.
• Experience with quality assurance practices and secure development in logic design.
• Experience delivering high-quality designs under tight deadlines and solving complex design challenges.

Culture & Benefits

• Work on next-generation AI hardware for edge and data center applications.
• Competitive pay with stock bonuses.
• Health, retirement, and vacation benefits.
• Opportunities to collaborate across multidisciplinary engineering teams.