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1 день назад

Senior VLSI Product and Test Engineer (AI)

Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Taiwan
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Senior VLSI Product and Test Engineer (AI): Developing and optimizing production test strategies for wafer-scale AI processors in high-volume manufacturing with an accent on ATE development, failure analysis, and yield improvement. Focus on building wafer-level test flows, isolating faults across massively parallel architectures, and optimizing voltage, thermal, power, and die-testing limits.

Location: Based in Taiwan with at least 50% travel within Taiwan

Company

hirify.global builds wafer-scale AI processors and high-performance computing systems designed to accelerate AI training and inference.

What you will do

  • Develop and optimize production test programs for wafer-scale AI processors.
  • Drive high-volume manufacturing testing with foundries and outsourced semiconductor assembly and test providers.
  • Implement design-for-test strategies, including scan, BIST, ATPG, and functional testing.
  • Analyze ATE, Shmoo, parametric, and defect data to improve yield and fault tolerance.
  • Develop failure-analysis and fault-isolation methods for defective cores, tiles, and functional blocks.
  • Support wafer and lot disposition while optimizing voltage-frequency limits, thermal behavior, power delivery, and parallel die testing.

Requirements

  • BS or MS in Electrical Engineering, Computer Engineering, or a related field.
  • 10+ years of semiconductor product or test-engineering experience supporting highly integrated devices.
  • Strong experience in test development, silicon debug, test optimization, and yield improvement.
  • Experience testing large parallel processors, GPUs, CPUs, or networking ASICs with SRAM, DDR/DRAM, or HBM.
  • Expert hands-on experience with the Advantest V93000 platform; Teradyne experience is a plus.
  • Experience designing and debugging load boards and probe cards, using Git-based development flows, and programming in C, C++, Python, or Perl.

Nice to have

  • Experience with Tessent, OBIRCH, IREM, LADA, or similar semiconductor failure-analysis techniques.
  • Experience testing high-speed SerDes and analog blocks embedded in digital ASICs.
  • Experience applying data analysis or machine-learning techniques to yield optimization.
  • Knowledge of wafer-scale packaging, TSVs, advanced interconnects, in-line diagnostics, and defect mitigation.

Culture & Benefits

  • Work on a wafer-scale AI platform designed beyond traditional GPU constraints.
  • Opportunities to contribute to cutting-edge AI research and open-source work.
  • Startup vitality with an emphasis on job stability.
  • Non-corporate work culture focused on individual perspectives, learning, growth, and support.

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