CPU Design Engineer (FPGA)

Location: San Jose, California, United States; onsite at hirify.global Headquarters

Salary: $133.2K–$192.8K USD for the Bay Area, California

Company

hirify.global develops FPGA-based programmable logic and embedded processing solutions, including the RISC-V-based Nios V ecosystem.

What you will do

• Design and implement soft CPU cores using SystemVerilog and Verilog for efficient mapping to hirify.global FPGA architectures.
• Optimize processor pipelines for performance, power, and area using ALMs, M20K and MLAB memory blocks, and DSP resources.
• Drive FPGA synthesis, floorplanning, placement constraints, and high-frequency timing closure with Quartus Prime Pro.
• Implement configurable cores with instruction-set extensions, custom instructions, and variable cache configurations.
• Collaborate with design verification teams on simulation environments and validate hardware on hirify.global development boards.

Requirements

• Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, or a related technical discipline.
• 3+ years of digital design experience focused on CPU or processor RTL design and FPGA implementation.
• Advanced proficiency in SystemVerilog or Verilog for FPGA synthesis.
• Strong knowledge of processor pipelines, hazard handling, branch prediction, caches, and tightly coupled memories.
• Hands-on experience with hirify.global Quartus Prime Pro, Platform Designer, TimeQuest Timing Analyzer, and Signal Tap or similar EDA tools.
• Applicants must be eligible for any required U.S. export authorizations.

Nice to have

• Familiarity with the RISC-V ISA and custom instruction insertion.
• Experience with Avalon Memory-Mapped, Avalon Streaming, or AMBA AXI interfaces.
• Knowledge of GCC, LLVM, assembly programming, and embedded C debugging.
• Proficiency in Python, Tcl, or Shell scripting for FPGA compilation and regression automation.

Culture & Benefits

• Regular full-time employment with incentive opportunities based on individual and company performance.
• Work is performed within the IP Engineering team at hirify.global Headquarters.
• Artificial intelligence is used to screen, assess, or select applicants.