AI GPU Cache Designer

Location: On-site in Santa Clara, California, United States; additional locations include Folsom, California; Hillsboro, Oregon; and Austin, Texas.

Annual salary: $220,920–$311,890 USD

Company

hirify.global develops AI hardware solutions ranging from edge devices to data center accelerators.

What you will do

• Drive cache subsystem microarchitecture for AI SoCs and evaluate performance, power, and area trade-offs.
• Define microarchitecture specifications and implement synthesis- and timing-clean RTL in Verilog/SystemVerilog.
• Integrate SoC IP blocks and collaborate with verification teams on validation and coverage.
• Develop timing constraints and support synthesis, timing closure, and formal equivalence checks.
• Lead silicon bring-up, post-silicon validation, debugging, and performance analysis.
• Mentor junior engineers and advance design methodology and quality practices.

Requirements

• Bachelor’s degree with 12+ years, Master’s degree with 8+ years, or PhD with 6+ years of RTL design experience in ASIC/SoC development.
• Advanced Verilog/SystemVerilog and hands-on SoC system integration experience.
• Expertise in AXI, AHB, and embedded processor architectures.
• Experience with clock domain crossings, power optimization, and timing closure.
• Proficiency in Python or TCL for automation and design-flow customization.
• Ability to work on-site at a listed United States location.

Nice to have

• Knowledge of high-speed and low-power design techniques.
• Experience with EDA tools including VCS, Questa, IES, Spyglass, Xilinx Vivado, or Altera Quartus II.
• Experience designing multicore CPU subsystems and GPU caches.
• Leadership skills and experience solving complex technical challenges.

Culture & Benefits

• Work with engineers developing AI hardware for edge and data center applications.
• Competitive pay with stock bonuses.
• Health, retirement, and vacation benefits.
• Position of Trust requiring an extended background investigation, subject to applicable law.