ASIC Implementation Engineer (AI)

Location: San Jose, California, USA; in-person work required with no remote option

Annual base salary: USD 143,800–230,000

Company

hirify.global develops semiconductor and ASIC solutions, including next-generation AI designs.

What you will do

• Execute physical design, physical verification, and timing closure from netlist to silicon tape-out.
• Perform top-level static timing analysis and apply timing-closure strategies.
• Handle electromigration and IR-drop analysis, place and route, floor-planning, and layout.
• Develop clock trees, including custom clock trees, insertion-delay reduction, and skew balancing.
• Develop physical-design flows and methodologies.
• Collaborate with IC design and RTL engineers.

Requirements

• Must work in person at the San Jose site; no remote work is allowed.
• 12+ years of relevant experience in physical design.
• Bachelor’s degree in Electrical Engineering or Electronics Engineering.
• Full physical-design-cycle experience from RTL to tape-out.
• Experience with TCL or Perl scripting and related EDA tools.
• Excellent verbal and written communication skills.

Culture & Benefits

• Annual discretionary bonus and new-hire and annual equity award opportunities.
• Medical, dental, and vision plans.
• 401(k) participation with company matching and an Employee Stock Purchase Program.
• Employee Assistance Program, paid holidays, paid sick leave, vacation, and applicable family-leave benefits.