Senior Director, Silicon Architecture and Design Engineering (PCIe)

Location: San Jose, California, United States

Salary: $231,500–$341,075 USD annually for the Bay Area California market

Company

hirify.global develops programmable device platforms and silicon technologies for AI, cloud, networking, storage, and edge applications.

What you will do

• Lead and scale a silicon engineering organization spanning design, SoC integration, and program execution.
• Own delivery of FPGA, ASIC, and SoC products across architecture, RTL design, verification, DFT, emulation, implementation, bring-up, validation, and production ramp.
• Set PCIe technical direction across controller architecture, PHY/SerDes integration, DMA, virtualization, verification, compliance, and interoperability.
• Define PCIe and CXL integration strategies for high-performance SoCs, including IP reuse, hard and soft IP partitioning, and hardware, firmware, and software co-design.
• Own customer-facing PCIe deliverables, including IP offerings, design-tool integration, reference designs, documentation, and design-in support.
• Partner with architecture, software, systems, product planning, manufacturing, customers, IP/EDA/foundry partners, PCI-SIG, and the CXL Consortium.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 15+ years of experience in silicon engineering, ASIC/SoC development, or FPGA product development.
• 10+ years of experience with PCIe and high-speed I/O technologies in compute, acceleration, storage, networking, or data-center infrastructure.
• Deep expertise in PCIe Transaction, Data Link, and Physical layers, including link training, ordering, flow control, enumeration, power management, error handling, and PHY/SerDes integration.
• Experience integrating PCIe controller and PHY subsystems into complex SoCs and delivering PCIe Gen4 and/or Gen5 designs into production silicon.
• Experience leading engineering managers and senior technical leads through production ramp.

Nice to have

• Master’s degree or PhD and experience with advanced process nodes and scaling silicon teams.
• PCIe Gen6/Gen7, PAM4, FLIT mode, forward error correction, advanced PHY/SerDes, retimers, and signal integrity.
• SR-IOV, ATS, PASID, PRI, IOMMU integration, peer-to-peer, RAS, and PCIe security.
• CXL.io, CXL.cache, CXL.mem, coherency, memory expansion, pooling, or accelerator connectivity.
• PCI-SIG compliance, FPGA architectures, performance modeling, UCIe, Ethernet, secure boot, or hardware root of trust.

Culture & Benefits

• Regular full-time employment on Shift 1 in the United States.
• Incentive opportunities based on individual and company performance.
• Work focused on multi-generation silicon roadmaps and high-performance interconnect technologies.
• Applicants must be eligible for any required U.S. export authorizations.