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3 дня назад

Senior Staff CAD Engineer (Semiconductor)

127 630 - 191 200$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Senior Staff CAD Engineer (Semiconductor): Developing and maintaining automated place-and-route flows, power grid implementations, and CAD add-on tools for advanced semiconductor designs with an accent on Cadence Innovus, 5nm-and-below nodes, and IR drop analysis. Focus on timing closure, floorplanning, routability, clock synthesis, power intent, signal integrity, and Tcl-based flow development.

Location: Santa Clara, California, United States

Salary: $127,630–$191,200 per year

Company

hirify.global develops semiconductor solutions for enterprise, cloud, AI, and carrier data infrastructure.

What you will do

  • Develop and maintain automated place-and-route flows for multiple business units.
  • Implement power grids across advanced technology nodes and ensure IR drop requirements are met.
  • Deploy, support, and integrate CAD flows into the broader CAD platform.
  • Develop add-on tools and innovative solutions for evolving semiconductor design challenges.
  • Track process and tool changes and collaborate with EDA vendors to optimize tool usage.

Requirements

  • Bachelor’s degree in Computer Science, Electrical Engineering, or a related field with 4+ years of relevant experience, or a Master’s degree/PhD with 3+ years of experience; equivalent professional experience may substitute for a degree.
  • At least 2 years of recent experience with Cadence Innovus.
  • Experience with 5nm-or-below advanced-node tape-outs, including FinFET, dual patterning, and ultra-low-voltage challenges.
  • Experience with power grid implementation and IR drop analysis.
  • Understanding of timing closure, floorplanning, routability, power grid validation, clock synthesis, SI, EM/IR, complex DRC rules, power intent, and multiple power domains.
  • Proficiency in Tcl scripting for flow development, strong analytical and problem-solving skills, and effective communication.

Nice to have

  • Experience with gate-to-gate equivalence checking, parasitic extraction, STA, physical verification, early rail analysis, and EM/IR flows.
  • Experience with implementation exploration methods and EDA tool benchmarking.

Culture & Benefits

  • Eligible for bonus and equity plans, including new-hire equity grants and annual equity refreshers.
  • Benefits support financial well-being, family support, mental and physical health, and recognition.
  • Additional offerings include an employee stock purchase plan, family support programs, mental health resources, and service awards.
  • Applicants must be eligible to access export-controlled technology under U.S. regulations; some applicants may require an export license review before employment.

Hiring process

  • Interviews assess individual experience, thought process, and communication skills in real time.
  • AI tools, transcription applications, automated answer generators, and automated note-taking tools are prohibited during interviews.

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