Graduate Talent (ISCP SoC Front End Team)

Location: Penang, Malaysia; hybrid work model with time split between the assigned hirify.global site and off-site work.

Company

hirify.global develops technologies and System-on-a-Chip solutions that power devices worldwide.

What you will do

• Design, develop, integrate, and verify proprietary SoC IPs.
• Use Verilog and SystemVerilog to validate IPs within broader SoC architectures.
• Collaborate with architects and cross-functional teams to ensure IP interoperability and compliance with design requirements.
• Develop test plans, simulations, and coverage analysis for functional validation.
• Debug pre-silicon validation and technical readiness issues.
• Create technical documentation, automate workflows, and improve SoC development processes.

Requirements

• Bachelor’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or a related field.
• Proficiency in hardware description languages such as Verilog or SystemVerilog.
• Knowledge of digital design, simulation, and verification methodologies.
• Experience with Python, Perl, or Shell scripting.
• Familiarity with EDA tools such as ModelSim or Synopsys VCS and industry-standard protocols.
• Strong analytical, problem-solving, communication, and teamwork abilities.

Culture & Benefits

• Hybrid work model combining on-site and off-site work.
• Shift 1 schedule in Malaysia.
• Opportunity to contribute to next-generation SoC technologies and hirify.global Client systems.
• Fast-paced environment focused on innovation and continuous learning.