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9 дней назад

Senior Staff IP Design Engineer (FPGA)

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Malaysia
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Senior Staff IP Design Engineer (FPGA/DSP): Designing and developing DSP-centric foundation IP blocks, RTL for FPGA hard macros and programmable DSP slices, and FPGA software tooling with an accent on filtering, FFT, fixed-point arithmetic, and sample-rate conversion. Focus on functional simulation, timing analysis, verification, and integrating DSP IP into simulation libraries and synthesis flows.

Location: Penang, Malaysia; proof of the right to work in Malaysia is required

Company

hirify.global develops low-cost, low-power programmable logic solutions, including FPGA, CPLD, and programmable power management devices.

What you will do

  • Design and implement DSP-centric foundation IP blocks, including multipliers, accumulators, FIR/IIR filter primitives, and arithmetic units for FPGA fabric.
  • Develop RTL in Verilog, VHDL, and SystemVerilog for DSP hard macros and programmable DSP slices.
  • Perform functional simulation and timing analysis to validate correctness and performance.
  • Collaborate with software and tools teams to model DSP IP in simulation libraries and synthesis flows.
  • Contribute to FPGA software release planning and execution, including requirements analysis, feature scoping, development, testing, and validation.
  • Maintain existing software product tools and improve test coverage and product quality.

Requirements

  • Bachelor’s or master’s degree in electronics/electrical engineering, computer engineering, or a related discipline.
  • 8 or more years of experience in IP design or ASIC/FPGA engineering.
  • Strong RTL design proficiency using Verilog, VHDL, or SystemVerilog.
  • Working knowledge of DSP theory and algorithms, including filtering, FFT, fixed-point arithmetic, and sample-rate conversion.
  • Successful background and reference checks, plus satisfactory proof of the right to work in Malaysia.

Nice to have

  • Experience with SystemVerilog Assertions and formal verification.
  • Familiarity with synthesis and static timing analysis tools such as Synopsys Design Compiler, PrimeTime, Radiant, or Quartus.
  • Knowledge of FPGA architectures and programmable DSP slice design.

Culture & Benefits

  • Work in an international engineering and manufacturing organization focused on R&D, product innovation, and customer service.
  • Collaborate in a fast-paced, results-oriented, team-first environment.
  • Access a comprehensive compensation and benefits program.
  • Work alongside a global workforce of approximately 1,000 employees.
  • Contribute to a workplace that values diversity of individuals, ideas, perspectives, insights, and values.

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