Physical Design Engineer (AI/ML)

Location: Hybrid, based in Austin, Texas; Fort Collins, Colorado; or Santa Clara, California, United States

Company

Develops high-performance AI platforms combining software models, compilers, networking, semiconductors, and RISC-V CPU technology.

What you will do

• Contribute to the physical design of high-performance chips for AI/ML architectures.
• Execute ASIC implementation from synthesis through signoff and tapeout.
• Optimize floorplanning, timing, power, performance, and area across multiple IPs.
• Work with front-end and physical design engineers across ASIC development.
• Contribute to clocking, I/O planning, timing closure, area improvement, and power optimization.
• Develop experiments and implementation flows to improve power, performance, and area.

Requirements

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Strong logic design fundamentals, including gate- and transistor-level implementation.
• Experience with synthesis, place-and-route flows, physical design tools, timing, EM/IR, and power analysis.
• Ability to work across floorplanning, clocking, I/O planning, timing closure, area improvement, and power optimization.
• Strong Tcl, Perl, Shell, and/or Python skills.
• Knowledge of low-power techniques including power gating, multi-Vt, and voltage scaling.

Culture & Benefits

• Collaborative environment with experienced engineers across ASIC disciplines.
• Opportunities to learn the complete ASIC implementation lifecycle and advanced AI/ML silicon development.
• Competitive compensation package and benefits.
• Employment is contingent on eligibility to access U.S. export-controlled technology and may depend on citizenship, permanent residence, or export-license approval.