6 дней назад
NAND Array Engineer (3D NAND)
139 520 - 255 000$
Мэтч & Сопровод
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Описание вакансии
Текст:
TL;DR
NAND Array Engineer (3D NAND): Designing and executing NAND memory cell and array characterization experiments while developing trims for next-generation memory products with an accent on array operation, reliability, device physics, and data analysis. Focus on optimizing Read Window Budget and Raw Bit Error Rate, building predictive models, driving wafer-level reliability experiments, and releasing improvements to high-volume manufacturing.
Location: Hybrid role based in San Jose, CA or Rancho Cordova, CA, United States
Salary: USD 139,520–255,000 yearly
Company
Global memory technology company developing advanced NAND products and data storage solutions.
What you will do
- Design and execute NAND memory cell and array characterization experiments covering erase, program, and read operations.
- Develop and optimize trims to improve Read Window Budget, Raw Bit Error Rate, product quality, and back-end test yields.
- Apply NAND device physics to interpret experimental data and explain relationships between device behavior and trim parameters.
- Collaborate with Device, Design, Reliability, Product, Test Engineering, and wafer fabrication teams on bench experiments and Sort/Wafer-Level Reliability DOEs.
- Analyze data, communicate parameter trade-offs, and build predictive models for NAND behavior.
- Maintain degradation scorecards and release optimized trims to production on a regular cadence.
Requirements
- Master’s or PhD in Electrical Engineering, Microelectronics, or a closely related field.
- At least 3 years of industry experience in semiconductor memory technologies and products.
- Deep understanding of NAND cell and array operations, reliability mechanisms, characterization techniques, semiconductor device physics, and process flows.
- Proficiency in statistical analysis methodologies and tools.
- Hands-on programming experience with C, C++, Python, and/or JMP.
- Strong analytical, problem-solving, communication, and cross-functional collaboration skills.
Nice to have
- Experience with 3D NAND architecture and advanced memory scaling challenges.
- Familiarity with wafer fabrication processes and Sort/WLR test methodologies.
- Experience releasing trims or process improvements to high-volume manufacturing.
- Experience with machine learning or advanced modeling techniques for semiconductor data.
Culture & Benefits
- Hybrid work arrangement from San Jose or Rancho Cordova, California.
- Eligibility for restricted stock units, restricted cash units, and cash bonus programs.
- Medical, dental, vision, life, AD&D, and disability insurance.
- Healthcare and dependent care flexible spending accounts.
- Company match on eligible 401(k) plan contributions.
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