Engineer II - Digital ASIC Design

Location: San Jose, California, United States; onsite at the Micrel R&D facility

Company

hirify.global develops semiconductor products and technology solutions through a large global engineering organization.

What you will do

• Implement RTL in SystemVerilog for complex digital IP blocks from micro-architecture through delivery.
• Optimize power, performance, and area to meet product targets.
• Collaborate with SoC integration teams on connectivity, timing, and congestion issues.
• Lead lint, CDC, RDC, and formal verification activities.
• Work with Physical Design teams on timing closure and routing bottlenecks.
• Verify and validate module and system functions, including post-silicon bring-up, and document design activities.

Requirements

• 2.5–5 years of experience in ASIC or FPGA digital design.
• Bachelor’s degree in Electrical Engineering.
• Proficiency in SystemVerilog and synchronous/asynchronous design techniques.
• Experience with the Cadence/Synopsys front-end EDA flow, including tools such as VCS, SpyGlass, Design Compiler, and PrimeTime.
• Familiarity with PHY or SerDes protocols; knowledge of IEEE 802.3 is beneficial.
• Scripting skills and experience with laboratory equipment such as oscilloscopes and logic analyzers.

Culture & Benefits

• Full-time position within a large global technology organization.
• Culture focused on trust, empowerment, respect, diversity, communication, and employee development.
• Leadership and career-development programs are available.
• Benefits are provided through Microchip’s employee programs.