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5 дней назад

Engineering IP Program Manager, Sr. Principal (Semiconductor)

173 280 - 259 600$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Engineering IP Program Manager, Sr. Principal (Semiconductor): Managing SoC IP development and delivery for product and custom silicon programs from conception through Mass Production Release with an accent on cross-functional engineering coordination, IP requirements, and advanced silicon development flows. Focus on leading distributed engineering program managers, managing risks and milestones, and driving closure across analog, logic, design-for-test, layout, timing, validation, and PnR activities.

Location: Santa Clara, California, United States

Salary: $173,280–$259,600 per year, plus eligibility for bonus and equity plans.

Company

hirify.global develops semiconductor solutions for enterprise, cloud, AI, carrier, product, and custom silicon infrastructure.

What you will do

  • Manage IP development and delivery for hirify.global product business units and custom silicon programs.
  • Drive closure of IP specifications and requirements from conception through Mass Production Release.
  • Lead cross-functional meetings covering status, milestones, risks, and plan completeness.
  • Provide regular program updates to executive stakeholders and support hirify.global’s program management process.
  • Provide matrixed leadership to engineering program managers across the organization.
  • Manage lessons learned, risks, process adherence, and successful IP delivery outcomes.

Requirements

  • Bachelor’s degree in Computer Science, Electrical Engineering, or a related field with 10–15 years of experience, or a master’s degree and/or PhD with 5–10 years of experience.
  • BS in Electrical Engineering is required; an MSEE is preferred.
  • 6+ years of experience as an Engineering Project Manager in the semiconductor industry is preferred.
  • 6+ years of experience as a mixed-signal IP designer.
  • Knowledge of SoC/IC design flows, advanced process technologies, process flows, and silicon development methodologies.
  • Broad ASIC or microelectronics development background, with strong leadership, communication, presentation, and stakeholder partnership skills.

Culture & Benefits

  • Employee stock purchase plan with a two-year lookback.
  • Bonus eligibility, new-hire equity grants, and annual equity refreshers.
  • Family support programs for balancing work and home life.
  • Mental and physical health resources.
  • Recognition and service awards.

Hiring process

  • Interviews assess individual experience, thought process, and communication skills in real time.
  • AI tools, transcription apps, automated answer generators, and automated note-taking bots are not permitted during interviews.
  • Access to export-controlled technology may require an export license review before employment.

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