7 дней назад
Director of SoC Implementation / Physical Design (Semiconductors)
Мэтч & Сопровод
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Описание вакансии
Текст:
TL;DR
Director of SoC Implementation / Physical Design (Semiconductors): Leading end-to-end physical design execution for advanced semiconductor SoCs from RTL to silicon with an accent on floorplanning, synthesis, place and route, signoff, and PPA optimization. Focus on delivering tapeout-ready designs at advanced technology nodes, scaling global physical design teams, and driving methodology and automation improvements.
Location: Austin (Oakhill, Office), United States
Company
Semiconductor products organization developing advanced SoCs for complex and high-reliability applications.
What you will do
- Lead end-to-end SoC physical design execution from RTL through tapeout and silicon.
- Own floorplanning, synthesis, place and route, clock-tree synthesis, routing, timing analysis, power delivery, physical verification, and signoff.
- Drive timing, power, IR/EM, physical verification, PPA, quality, and cost-efficiency closure.
- Plan and execute physical design programs, managing risks, dependencies, schedules, and delivery across global sites.
- Build and lead global physical design teams, including hiring, mentoring, career development, and performance tracking.
- Define advanced-node methodologies, improve automation and flows, and collaborate with architecture, RTL, verification, packaging, EDA, and IP teams.
Requirements
- Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or a related field.
- 17+ years of experience in ASIC or SoC physical design.
- Experience leading large-scale SoC programs and global technical teams.
- Strong knowledge of Synopsys and Cadence EDA flows.
- Experience with RTL-to-GDSII implementation, STA, EM/IR, PDN, signal integrity, physical verification, and low-power design using UPF or CPF.
- Ability to work from the Austin (Oakhill) office.
Nice to have
- Experience with automotive or high-reliability SoCs.
- Expertise in chip-level PDN, EMIR, and signal-integrity closure.
- Experience leading global teams across multiple geographies.
- Exposure to AI-driven design methodologies and automation.
Culture & Benefits
- Cross-functional collaboration with architecture, RTL, verification, product, packaging, EDA, and IP teams.
- Interaction with senior leadership on status reporting, escalation, and technical decisions.
- Opportunity to work on advanced technology nodes, including 5nm and beyond.
- Equal opportunity employment and reasonable accommodations for qualified individuals with disabilities.
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