Physical Design Intern (Semiconductor)

Location: Singapore

Company

hirify.global develops ultra-low-power semiconductor solutions for wearables, medical devices, IoT products, and AI-powered edge applications.

What you will do

• Support block-level physical implementation for SoC designs.
• Assist with floorplanning, placement, clock tree synthesis, routing, and timing closure.
• Run static timing analysis and debug setup and hold violations.
• Help analyze power, signal integrity, and IR drop under engineering guidance.
• Contribute to DRC and LVS closure activities.
• Develop Tcl, Python, and Shell scripts to automate recurring tasks, document results, and collaborate with RTL, verification, and physical design engineers.

Requirements

• Currently pursuing a B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
• Coursework in digital logic design and VLSI, physical design, or ASIC design.
• Familiarity with Verilog or VHDL and digital design concepts, including timing, pipelining, and clocking.
• Basic understanding of placement, routing, timing closure, clock trees, and power grid planning.
• Comfortable working in a Linux/UNIX environment.

Nice to have

• Coursework in computer architecture.

Culture & Benefits

• Hands-on experience with industry-standard physical implementation tools.
• Opportunity to work alongside experienced engineers on ultra-low-power chip tapeouts.
• Mentorship, progress presentations, and exposure to complex semiconductor development work.