Senior Director, Silicon Architecture and Design Engineering (Ethernet)

Location: San Jose, California, United States

Salary: $231,500–$341,075 USD annually for the Bay Area California location. Incentive opportunities are also available.

Company

hirify.global develops programmable device technologies, including FPGA, ASIC, and SoC platforms for AI, cloud, networking, and edge applications.

What you will do

• Lead the Ethernet Center of Excellence and define the technical direction, architecture, methodologies, and multi-generation Ethernet roadmap.
• Lead, grow, and mentor a global silicon engineering organization delivering FPGA, ASIC, and SoC products.
• Direct end-to-end silicon execution across product definition, microarchitecture, RTL, verification, DFT, emulation, implementation, bring-up, validation, and production.
• Define Ethernet architectures covering MAC, PCS, FEC, auto-negotiation, link training, and high-speed PHY/SerDes integration.
• Guide networking datapath architecture, including packet processing, L2/L3 forwarding, QoS, traffic management, buffering, scheduling, congestion management, and telemetry.
• Drive complex silicon programs, partner with customers, standards bodies, foundries, IP and EDA providers, and align architecture, software, systems, product planning, and manufacturing teams.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science.
• 15+ years of experience in silicon engineering, ASIC, SoC, or FPGA product development.
• 10+ years of experience with networking and Ethernet technologies, including architecture or silicon and product development for networking, switching, interconnect, or data center infrastructure.
• Deep expertise in IEEE 802.3 Ethernet architecture from MAC/PCS through high-speed PHY/SerDes integration.
• Experience with multiple generations of high-speed Ethernet through 800G-class and AI/data-center scale-out networking, including technologies such as RDMA/RoCE, lossless Ethernet, congestion control, or Ultra Ethernet.
• Applicants must be eligible for any required U.S. export authorizations.

Nice to have

• Master’s degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
• Experience with advanced process nodes, high-complexity SoCs or ASICs, and building new teams.
• Experience with emerging 1.6T Ethernet, 112G/224G-class SerDes, FPGA or heterogeneous SoC platforms, Ethernet IP, transceiver integration, and third-party PHY/controller IP.

Culture & Benefits

• Regular full-time employment with incentive opportunities based on individual and company performance.
• Collaboration with hyperscale, networking, and AI infrastructure customers, ecosystem partners, standards bodies, foundries, IP providers, and EDA partners.
• Work on programmable silicon technologies supporting AI, cloud, networking, and edge applications.