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7 дней назад

Principal ASIC Chip Lead

143 800 - 230 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior/lead
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR
Principal ASIC Chip Lead (ASIC/SoC): Leading end-to-end ASIC and SoC development from microarchitecture and Verilog RTL through verification, GDSII tape-out, silicon bring-up, and mass production with an accent on low-power design, timing closure, and cross-functional execution. Focus on defining complex design blocks, closing verification and physical-design requirements, and coordinating FPGA and silicon bring-up with customer-facing project teams.

Location: USA-CA San Jose Innovation Drive

Annual base salary: USD 143,800–230,000

Company

hirify.global develops semiconductor and system-on-chip solutions.

What you will do

  • Lead end-to-end ASIC and SoC development from architecture and RTL through GDSII tape-out and mass production.
  • Manage cross-functional project teams and interface directly with a tier-one customer.
  • Define microarchitecture and develop Verilog RTL for design blocks.
  • Run frontend checks including linting, clock-domain crossing, and low-power flows using UPF/CPF.
  • Coordinate verification plans, coverage closure, physical-design constraints, timing closure, and FPGA or silicon bring-up.
  • Support operations in bringing silicon into mass production and take on additional design or verification responsibilities as needed.

Requirements

  • 12+ years of experience with a BSEE or 10+ years with an MSEE in microarchitecture and RTL design.
  • Strong RTL and logic-design skills using Verilog HDL.
  • Detailed knowledge of logic synthesis, static timing analysis, design verification, clock-domain crossing, low-power design, and multiple power domains.
  • Experience with EDA tools, UPF/CPF flows, ARM-based SoCs, DSP-based designs, peripherals, memory controllers, and AHB or AXI interconnects.
  • Excellent written and verbal communication skills and the ability to understand engineering and microarchitecture specifications.
  • Onsite work in San Jose, California, USA.

Nice to have

  • Experience with analog interfaces, arithmetic hardware, MATLAB/Simulink, signal processing, and numerical analysis.
  • Experience using logic analyzers and oscilloscopes during FPGA or silicon bring-up.
  • Experience with C/C++ and Perl or Tcl scripting.
  • Experience utilizing AI tools.

Culture & Benefits

  • Discretionary annual bonus and new-hire and annual equity awards.
  • Medical, dental, and vision plans.
  • 401(k) participation with company matching and an Employee Stock Purchase Program.
  • Employee Assistance Program, paid holidays, paid sick leave, vacation time, and applicable family-leave benefits.
  • Equal opportunity employment in accordance with applicable federal, state, and local laws.

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