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8 дней назад

Senior Principal Engineer AI/ML

171 000 - 325 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Senior Principal Engineer AI/ML (RISC-V CPU Architecture): Defining and leading RTL development for an AI-enabled RISC-V CPU core and matrix engine with an accent on microarchitecture, vector processing, and power, performance, and area optimization. Focus on designing high-performance CPU blocks, developing detailed specifications, supporting functional verification, and validating physical design constraints.

Location: Santa Clara, United States; onsite role

Salary: $171,000–$325,000 per year

Company

hirify.global is a semiconductor foundry providing chip design, development, and fabrication services through a global manufacturing footprint.

What you will do

  • Define, lead, and own RTL development for an AI-enabled RISC-V CPU core.
  • Drive microarchitecture and design critical CPU blocks, including vector processing and custom extensions.
  • Design an AI-enabled matrix engine to augment the vector CPU.
  • Explore high-performance strategies with the CPU modeling team and develop specifications from architectural exploration through detailed microarchitecture.
  • Refine RTL designs against power, performance, area, and timing goals.
  • Support functional verification and collaborate on physical design validation covering timing, area, reliability, testability, and power.

Requirements

  • Master’s degree with 10+ years of experience or PhD with 5+ years of work experience.
  • Hands-on knowledge of in-order or out-of-order high-performance CPU pipeline stages.
  • Expertise in microprocessor architecture, including areas such as instruction processing, branch prediction, scheduling, register renaming, execution units, caches, memory subsystems, or vector datapaths.
  • Knowledge of cache coherency, memory consistency, logic design, and timing and power implications.
  • Knowledge of SystemVerilog, Verilog, and/or VHDL, plus experience with simulators and waveform debugging tools.
  • Ability to collaborate with multifunctional engineering teams on CPU and physical design implementation.

Nice to have

  • Experience designing RISC-V, ARM, or MIPS CPUs.
  • Experience with hardware multithreading, virtualization, SIMD, and vector- or matrix-enabled CPUs.
  • Knowledge of low-power microarchitecture, CPU integration at the SoC level, and safety and security microarchitecture.
  • Experience with Perl or Python scripting.

Culture & Benefits

  • Full-time employment with a semiconductor technology company.
  • Work in a multifunctional engineering environment spanning CPU modeling, verification, and physical design.
  • Commitment to environmental, health, safety, and security requirements.
  • Equal opportunity workplace with reasonable accommodation available during the employment process.

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