Senior Staff Digital Design Engineer (ASIC)

Location: Irvine, CA, United States

Base pay: $135,900–$201,130 per annum

Company

hirify.global develops semiconductor solutions and connectivity silicon for enterprise, cloud, AI, carrier, and data-center infrastructure.

What you will do

• Define SoC-level specifications and translate product and protocol requirements into microarchitecture for datapaths, DSP pipelines, subsystems, and IP blocks.
• Develop synthesizable SystemVerilog RTL and drive ASIC front-end flows including lint, CDC/RDC, synthesis, timing constraints, and design-for-test readiness.
• Lead digital logic integration, reusable and parameterized design development, timing closure, floorplanning support, congestion analysis, and optimization across advanced process nodes.
• Collaborate with design verification, physical design, firmware, systems, and architecture teams on verification strategies, coverage, power-aware validation, and tape-out execution.
• Support emulation, FPGA prototyping, performance modeling, post-silicon bring-up, lab validation, and debug of datapath, DSP, and protocol issues.
• Mentor engineers, participate in design and microarchitecture reviews, and influence design and verification methodology.

Requirements

• Extensive experience in digital ASIC design, microarchitecture, RTL implementation, and complex logic integration.
• 3–10+ years of industry experience with large-scale ASICs; typical requirements are 5–10+ years with a bachelor's degree or 3–5+ years with a master's degree or PhD.
• Strong experience with high-performance DSP, high-speed datapaths, pipelined arithmetic, packet processing, memory subsystems, and large-scale control logic.
• Knowledge of Ethernet protocols and networking standards, including MAC, PCS framing, flow control, and packet-level behavior.
• Proficiency with lint, CDC/RDC, synthesis, static timing analysis, and power/performance optimization, plus experience with advanced process nodes such as 5nm or 3nm.
• BS/MS in Electrical Engineering, Computer Engineering, or a related field; communication, leadership, mentoring, and cross-functional collaboration skills are required. Applicants must be eligible to access U.S. export-controlled technology; export license review may apply.

Nice to have

• DSP algorithm implementation involving adaptive equalization, channel estimation, and high-throughput filtering.
• Experience with FEC architectures such as LDPC, RS, or BCH.
• PHY design experience with PMA DSP pipelines, equalization, clock recovery, or SerDes-adjacent logic.
• PhD in a related field.

Culture & Benefits

• Work on connectivity silicon supporting AI-scale data centers and next-generation Ethernet and optical interconnects.
• Bonus and equity plan eligibility, including a new-hire equity grant and annual equity refreshers.
• Employee stock purchase plan with a two-year look-back.
• Family support programs, mental and physical health resources, and recognition and service awards.

Hiring process

• Interview process evaluates individual experience, reasoning, and communication in real time.
• AI tools, transcription apps, automated note-taking bots, and real-time answer generators are not permitted during interviews.