IC Verification Engineer

Location: Onsite in San Jose, California, United States

Annual base salary: USD 143,800–230,000

Company

A semiconductor technology company developing complex integrated circuit and system solutions.

What you will do

• Architect and develop scalable, reusable testbench environments using verification methodologies.
• Create test plans and functional coverage for block, core, and SoC features.
• Build pseudo-random tests, drive verification to closure, and analyze coverage gaps.
• Debug regression failures and improve test quality and verification efficiency.
• Document verification strategies, environments, and tests, and lead design and architecture reviews.
• Collaborate with the team and guide junior verification engineers.

Requirements

• Bachelor’s degree in Electrical Engineering, Electronics, or an equivalent field with 12+ years of relevant experience, or a master’s degree with 10+ years of relevant experience.
• 10+ years of experience developing complex verification environments, test plans, functional coverage, and pseudo-random tests.
• Experience leading verification through a complete ASIC cycle from architecture development to tapeout.
• Strong proficiency in SystemVerilog and verification methodologies such as UVM and VMM.
• Strong debugging skills and the ability to analyze regression failures and complex designs.
• Understanding of complex multi-layered protocols such as PCI Express.

Nice to have

• Experience with PCIe protocol verification.
• Comfort with Makefiles.
• Experience verifying protocols such as AXI.

Culture & Benefits

• Discretionary annual bonus and new-hire and annual equity awards.
• Medical, dental, and vision plans.
• 401(k) participation with company matching and an Employee Stock Purchase Program.
• Paid holidays, sick leave, vacation time, and applicable family and other leaves of absence.
• Employee Assistance Program and equal opportunity employment practices.