Rack-Scale AI Hardware Architect

Location: Austin, TX / Palo Alto, CA; hybrid workplace

Company

hirify.global develops energy-efficient AI compute platforms built from large numbers of small accelerators.

What you will do

• Own rack-level reference architecture across boards, chassis, backplanes, topology, mechanical constraints, and serviceability.
• Design scale-up and scale-out interconnects using PCIe, high-speed Ethernet, SerDes, copper and optical links, retimers, connectors, and cable plants.
• Develop thermal architectures for high-density racks, including direct-to-chip cooling, cold plates, immersion, CDUs, manifolds, and facility interfaces.
• Define power delivery architecture covering rack distribution, busbars, high-voltage DC, 48V-class conversion, redundancy, telemetry, and reliability.
• Model LLM partitioning, inter-layer traffic, collectives, performance, power, thermal behavior, and cost with the software team.
• Carry reference designs from pathfinding through working implementations, ODM/OEM production, and customer deployment.

Requirements

• Bachelor’s degree in Electrical Engineering, Mechanical Engineering, Computer Engineering, or a related field.
• Relevant experience designing server, datacenter, HPC, or AI systems.
• Ownership of dense rack-based server systems taken to production, including specifications for ODM and OEM partners.
• Expertise in copper and optical interconnects, PCIe, high-speed Ethernet, SerDes, DAC, twinax, backplanes, cabled channels, AOCs, and optical modules.
• Expertise in rack cooling, cold plates, manifolds, CDUs, flow and thermal budgets, and facility-side interfaces.
• Ability to make architecture and trade-off decisions across interconnect, power, thermal, mechanical, and software domains.

Nice to have

• Master’s degree or PhD in a relevant engineering field.
• Hyperscale or OCP experience, including ORv3 and standards contributions.
• Experience with many-accelerator, dataflow, wafer-scale, chiplet, die-to-die, or advanced-packaging systems.
• Experience with large-scale LLM training or inference and parallelism strategies.
• Experience taking reference designs through ODM or contract manufacturing partners and qualification.

Culture & Benefits

• Work across silicon, packaging, systems, software, firmware, and product strategy.
• Collaborate on difficult engineering problems spanning the full AI hardware stack.
• Hold a senior individual-contributor role with broad technical visibility and influence.
• Join an inclusive team that encourages candidates from all backgrounds to apply.