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6 дней назад

High Performance Compute Responsible Engineer (Aerospace)

175 000 - 263 000$
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR
High Performance Compute Responsible Engineer (Aerospace): Designing and validating high-performance compute boards for onboard AI/ML inference and science data processing with an accent on power delivery, high-speed digital interfaces, and board-level validation. Focus on architecting 500W+ multi-rail systems, debugging PCIe Gen 4/5 and DDR5 or HBM interfaces, and bringing up hardware in collaboration with software engineers.

Location: Long Beach, California, United States

Hiring range: $175,000–$263,000 USD annually

Company

Develops rockets, launch vehicles, factories, and space-science systems, including the Terran R vehicle and the Interplanetary Sciences Program.

What you will do

  • Own compute hardware from architecture and component selection through schematic capture, board bring-up, and validation.
  • Design compute boards delivering at least 10 TFLOPS for onboard AI/ML inference and science data processing.
  • Architect 500W+ multi-rail power delivery networks with tight sequencing for GPU and CPU compute modules on custom PCBs.
  • Define thermal interface requirements, including power budgets, junction temperature limits, and interface material specifications.
  • Design and validate HBM, DDR5, PCIe Gen 4/5, and 10 GbE+ interfaces, plus power monitoring, current limiting, and radiation upset recovery circuitry.
  • Lead hands-on hardware bring-up and board-level debugging with software engineers.

Requirements

  • BSEE and 5+ years of experience designing and bringing up high-speed digital compute boards.
  • Experience with high-speed digital PCB design, multi-GHz signaling, dense BGA escape routing, high-layer-count stackups, and signal-integrity analysis through simulation and measurement.
  • Strong power-integrity and power-delivery expertise, including multi-rail architectures, PMIC selection, voltage sequencing, and board-level current limiting.
  • Hands-on experience designing, analyzing, and debugging high-speed serial interfaces, especially PCIe Gen 4/5 and Ethernet.
  • Direct exposure to GPU, HPC, or modern accelerator platforms is preferred.

Nice to have

  • Basic firmware development for hardware bring-up and validation.
  • Embedded-systems debugging and hands-on bench problem-solving.
  • Experience with COTS hardware for space applications, radiation awareness, component derating, ECC memory scrubbing, and watchdog or reset architectures.
  • Physical PCB layout experience with complex, high-layer-count boards and dense BGA packages.
  • Board- and system-level thermal-management experience and collaboration with mechanical engineers on packaging solutions.

Culture & Benefits

  • Work emphasizes autonomy, ownership, cross-functional collaboration, and technical rigor.
  • Competitive salary and equity compensation.
  • Generous paid time off and sick leave.
  • Parental leave and an annual learning and development stipend.

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