Analog Layout Intern, BS - Summer 2027 (Semiconductor)

Location: Santa Clara, California, United States

Salary: $28–$56 per hour

Company

hirify.global develops semiconductor solutions for enterprise, cloud and AI, carrier, automotive, storage, security, and networking infrastructure.

What you will do

• Translate analog IC schematics into physical layouts using Cadence Virtuoso.
• Implement microelectronic layers for advanced semiconductor technologies.
• Run design rule checks, layout-versus-schematic checks, and other physical verification flows.
• Collaborate with Analog IC Designers to debug and refine layouts against target specifications.
• Present progress and technical findings in team meetings and cross-functional project reviews.
• Contribute to semiconductor IP development and real product tapeouts across advanced process nodes such as TSMC N2 and N3.

Requirements

• Currently pursuing a Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
• Expected graduation between Fall 2027 and Summer 2028.
• Fundamental understanding of electrical engineering, analog circuit theory, and microelectronics.
• Coursework or hands-on experience in analog design, IC layout, or VLSI design.
• Familiarity with Cadence Virtuoso, Calibre, or similar EDA tools.
• Eligibility to access export-controlled technology and software under applicable U.S. export control regulations may be required.

Culture & Benefits

• Work with a small, high-impact analog layout team and global colleagues across Argentina, Singapore, the United States, and Europe.
• Contribute to real products and tapeouts while learning across engineering disciplines.
• Medical, dental, and vision coverage for interns.
• Perks and discounts, mental health resources, and paid holidays.
• Additional compensation may be available for intern PhD candidates.

Hiring process

• Interviews evaluate individual experience, thought process, and communication skills in real time.
• Use of AI tools, transcription apps, automated answer generators, or note-taking bots is prohibited during interviews.