Senior Analog Layout Designer (Semiconductor)

Location: Austin, Texas, United States; on-site

Salary: Starting from $292,000 annually

Company

hirify.global develops the DX-1 decode accelerator through rack-scale co-design of logic, data movement, packaging, optics, and interconnect.

What you will do

• Create layouts for RX/TX lane macros and support lane-level integration.
• Own major analog layout macros, including ADC, DAC, TIA, CDR, PLL, BGB, and LDO designs.
• Perform block and macro floor-planning, integration, routing, clock distribution, and power grid implementation.
• Apply layout techniques for device matching, symmetry, parasitic reduction, noise isolation, ESDs, and clamps.
• Run and debug LVS, ERC, DRC, density, DFM, antenna, and EM/IR verification.
• Support tape-outs, revision-controlled design libraries, and lane integration.

Requirements

• 7+ years of analog layout design experience.
• At least 3 years of experience with TSMC 2nm, 3nm, 4nm, and 5nm FinFET processes.
• Several FinFET tape-outs with ownership of major layout macros.
• Expert knowledge of floor-planning, block integration, routing, clock distribution, power grids, matching, parasitic reduction, noise isolation, and EM/IR analysis.
• Expertise with Cadence Virtuoso and Calibre or Pegasus verification tools.
• Eligibility is subject to U.S. export control regulations and recent citizenship or permanent residency status; applicants from certain restricted countries may be ineligible.

Nice to have

• Knowledge of SKILL, TCL, and Python scripting.

Culture & Benefits

• Meaningful stock options and ownership participation.
• Annual living-local bonus for residences within 20 minutes of the office.
• Employer-contributed retirement plans.
• Competitive compensation based on experience, skills, and location.