Staff Engineer, Analog Layout

Location: Singapore; onsite five days per week

Company

hirify.global develops ultra-low-power semiconductor solutions for wearables, medical devices, IoT products, and AI-powered edge applications.

What you will do

• Partner with analog designers on chip-level and block-level floorplanning and layout strategy.
• Drive layout architecture decisions balancing performance, matching, area, and reliability.
• Execute transistor-level analog IC layout, including critical matching, shielding, and parasitic-sensitive structures.
• Lead layout for complex blocks and review work from other layout engineers.
• Own parasitic extraction, LVS, DRC, antenna, and fill closure for assigned blocks and top-level integration.
• Support prototype bring-up, manufacturing test planning, production needs, yield, and customer questions related to layout.

Requirements

• Experience across the full analog layout flow, from floorplanning and designer collaboration through detailed layout, parasitic extraction, LVS/DRC closure, tape-out, validation, and production test support.
• Experience with analog subsystems such as PMUs, clocking, and data converters.
• Ability to work with analog design and RTL/physical design teams to preserve circuit intent and interface requirements.
• Experience with leading-edge technologies such as 22nm and 12nm.
• Ability to work onsite in Singapore five days per week.

Culture & Benefits

• Cross-functional collaboration across design, research, development, production, marketing, sales, and operations.
• Work on complex semiconductor projects focused on energy efficiency and AI at the edge.
• Company values include innovation, collaboration, focus, learning, and achievement.