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4 дня назад

Senior Physical Design Engineer (ASIC)

109 000 - 174 000CAD
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Canada
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR
Senior Physical Design Engineer (ASIC): Developing large mixed-signal SoC ASICs for optical networking products with an accent on physical architecture, timing closure, and power, performance, and area optimization. Focus on building RTL-to-GDSII flows, designing floorplans and clock distribution networks, resolving timing and DFT challenges, and automating backend engineering workflows.

Location: Ottawa, Canada

Salary: CAD 109,000–174,000 per year

Company

hirify.global develops high-speed connectivity infrastructure and optical fiber transmission solutions for the telecommunications industry.

What you will do

  • Define physical architectures and maintain robust netlist-to-GDSII implementation flows using EDA tools.
  • Create floorplans, power grids, and clock distribution networks optimized for performance, power, and area.
  • Run Place & Route trials, static timing analysis, timing and functional ECOs, and timing closure activities.
  • Integrate analog blocks into large mixed-signal SoC ASICs with analog, RTL, and ASIC/SoC teams.
  • Resolve DFT timing challenges through scan chain reordering, placement, and CTS constraint management.
  • Develop automation scripts, analyze formal verification reports, and collaborate with EDA vendors to improve workflows.

Requirements

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related scientific discipline, plus significant ASIC physical design and timing closure experience.
  • Understanding of submicron technology nodes, the full backend ASIC flow, and timing, power, and area trade-offs.
  • Proven experience with Place & Route tools and backend-flow automation scripting.
  • Understanding of UPF and SOCV/POCV concepts.
  • Experience with physical design of large mixed-signal SoC ASICs and advanced technology nodes.

Nice to have

  • Experience with multiple power domains, physical verification using Calibre, and power integrity analysis such as EMIR.
  • Hands-on experience creating and validating timing constraints and performing Static Timing Analysis.
  • Experience with physical synthesis and complete RTL-to-GDS flows using industry-standard EDA tools.

Culture & Benefits

  • Collaborative environment spanning RTL, analog, ASIC/SoC, layout, architecture, and tool-vendor teams.
  • Medical, dental, and vision coverage.
  • Canada DCPP with company matching and an Employee Stock Purchase Program.
  • Company-paid holidays, paid sick leave, vacation time, and applicable family and other leave benefits.
  • Employee Assistance Program and opportunities for professional development.

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