Midcore Design Verification Engineer (RISC-V)

Location: Remote, based in North America or Spain

Compensation: $100,000–$500,000, including base and variable compensation targets.

Company

Tenstorrent develops high-performance AI computing platforms combining software, compilers, networking, and RISC-V semiconductor technology.

What you will do

• Develop verification strategies and test plans for next-generation, high-performance RISC-V CPU cores.
• Architect robust test benches using SystemVerilog and UVM.
• Build constrained-random tests, assertions, and functional coverage.
• Debug RTL and simulation failures with waveforms and simulation/debug tools.
• Identify root causes, uncover processor corner cases, and drive issues to closure.
• Collaborate with CPU architects, RTL designers, software engineers, and verification engineers.

Requirements

• 6+ years of design verification experience for CPUs, SoCs, ASICs, or other complex digital designs.
• Strong experience with SystemVerilog and UVM.
• Understanding of CPU architecture or microarchitecture, including pipelines, out-of-order execution, caches, load/store, branch prediction, or instruction scheduling.
• Experience debugging RTL and simulation failures using waveforms and common simulation/debug tools.
• Strong C, C++, or Python skills.
• Employment is contingent on eligibility to access U.S. export-controlled technology.

Nice to have

• Experience verifying processor pipelines and interacting subsystems.
• Interest in RISC-V, AI, HPC, and high-performance computing systems.

Culture & Benefits

• Remote work based in North America or Spain.
• Competitive compensation package and benefits.
• Collaborative environment focused on curiosity and solving complex technical problems.
• Hands-on exposure to the full CPU design lifecycle from specification through silicon.