SoC Micro-Architect & RTL Designer (AI)

Location: Hybrid in Mountain View, California; on-site Tuesday through Thursday. Candidates must be authorized to work in the United States.

Salary: $200,000+ base salary plus RSUs

Company

Well-funded AI semiconductor startup developing a processor architecture for frontier-scale language-model training and inference.

What you will do

• Translate processor architecture requirements into production-quality microarchitecture and RTL.
• Own blocks or subsystems from specification through sign-off.
• Develop compute, memory-management, or high-speed-connectivity functionality.
• Optimize performance, power, area, and timing.
• Collaborate with verification, DFT, physical design, architecture, and software teams.
• Support silicon bring-up and post-silicon debug.

Requirements

• 5+ years of SoC or ASIC microarchitecture and RTL-design experience.
• Strong SystemVerilog skills and experience with Python or C/C++.
• Experience taking complex designs toward production silicon.
• Hands-on knowledge of synthesis, lint, CDC, and equivalence checking.
• Experience delivering high-performance compute, memory, or connectivity designs.
• Understanding of how RTL decisions affect timing, power, area, and physical implementation.

Nice to have

• PCIe, HBM, DMA, or die-to-die subsystem experience.
• CPU, GPU, or machine-learning accelerator experience.
• Emulation, silicon bring-up, or post-silicon debug experience.
• Ownership of a complete subsystem through tape-out.

Culture & Benefits

• Opportunity to influence architectural and implementation decisions before conventions are fixed.
• Work on a processor co-designed for the throughput, latency, memory, and interconnect demands of large-model training and inference.
• RSU-based equity in addition to the base salary.