Sr. Staff Engineer, RTL Physical Implementation Lead (AI)

Location: Hybrid, based in Austin, Texas, or Santa Clara, California, United States

Company

Tenstorrent develops high-performance AI platforms combining software models, compilers, networking, platforms, semiconductors, and RISC-V CPUs.

What you will do

• Lead front-end RTL physical implementation and define PPA targets for high-performance RISC-V CPUs and subsystems.
• Drive CAD flows across multiple process technologies and develop initial floorplans with early area, power, and frequency estimates.
• Collaborate with CPU microarchitects and RTL designers to optimize frequency, power, and area across process nodes.
• Partner with physical design teams to improve and standardize methodologies, flows, and IP collateral.
• Run physical design experiments, evaluate results, and communicate PPA trade-offs and recommendations.
• Collaborate with design verification, physical design, RTL, and performance teams to deliver timing- and power-converged designs.

Requirements

• Expertise in physical design practices for PPA optimization and high-performance physical design.
• Proficiency in RTL coding with Verilog or VHDL.
• Experience with industry-standard simulation and power analysis tools.
• Strong knowledge of synthesis, place-and-route tools, physical design flows, and methodology.
• Background in CPU microarchitecture, preferably involving RISC-V designs.
• Eligibility to access U.S. export-controlled technology is required; employment may depend on citizenship, permanent residency, or prior license approval.

Culture & Benefits

• Highly technical and collaborative environment focused on solving difficult CPU design challenges.
• Opportunity to develop and lead a physical design team.
• End-to-end exposure to CPU design from microarchitecture through timing and power convergence.
• Hands-on work integrating open-source and industry-standard tools to improve physical design flows.
• Competitive compensation package and benefits.