Sr. Engineer, RTL Implementation (AI)

TL;DR

Sr. Engineer, RTL Implementation (AI): Developing and optimizing high-performance RISC-V CPU cores for cutting-edge AI platforms with an accent on physical design, synthesis, and PPA optimization. Focus on iterating through front-end CAD flows, collaborating with micro-architects, and driving timing and power convergence for complex semiconductor designs.

Location: Hybrid, must be based in or able to work from Austin, TX or Santa Clara, CA

Compensation: $100,000–$500,000

Company

hirify.global is a leading AI hardware and software company building high-performance RISC-V CPU and AI platforms to redefine computing paradigms.

What you will do

• Perform synthesis and initial place and route for new and legacy CPU designs.
• Collaborate with core micro-architects to optimize core configurations for best PPA.
• Drive physical design experiments to optimize power, performance, and area.
• Enhance physical design environments, tools, and methodologies to improve efficiency.
• Work closely with DV, PD, RTL, and performance teams to deliver converged designs.

Requirements

• Must be eligible to access U.S. export-controlled technology (EAR compliance).
• Experience in high-performance physical design.
• Proficiency in RTL coding (Verilog/VHDL) and industry-standard simulation tools.
• Skilled in synthesis and place and route tools.
• Background in CPU micro-architecture.

Culture & Benefits

• Competitive compensation package including base and variable targets.
• Opportunity to work on cutting-edge RISC-V and AI technology.
• Highly collaborative and deeply technical team environment.
• Equal opportunity employer with a focus on solving hard, industry-defining problems.