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4 дня назад

Principal Physical Design Engineer (AI)

300 000 - 400 000$
Формат работы
remote (только USA)/onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR
Principal Physical Design Engineer (AI): Owning the complete physical implementation of critical blocks for a high-performance AI accelerator SoC from floorplanning through final tapeout signoff with an accent on place and route, clock tree synthesis, timing closure, power optimization, and physical verification. Focus on developing AI-assisted implementation methodologies, optimizing performance, power, and area, and resolving complex implementation challenges with EDA vendors and foundry partners.

Location: US-based opportunities including Mountain View, Boulder, the San Francisco Bay Area, San Mateo, Virginia, and remote work across Eastern and Central Time Zones in the US; onsite work is available in the Bay Area.

Salary: $300,000–$400,000 annually, with additional equity participation.

Company

Early-stage AI hardware startup building a next-generation inference platform that combines custom silicon with integrated software and systems engineering.

What you will do

  • Own the complete physical design flow for major SoC blocks from floorplanning through final signoff.
  • Drive place and route, clock tree synthesis, timing closure, power optimization, and physical verification.
  • Develop and apply AI-assisted implementation methodologies to improve productivity and accelerate tapeout schedules.
  • Partner with architecture, RTL, verification, and software teams to optimize performance, power, and area.
  • Collaborate with EDA vendors and foundry partners to resolve implementation challenges and deliver production-ready silicon.

Requirements

  • 8+ years of physical design experience for complex, high-performance ASICs at advanced process nodes of 7nm or below.
  • Deep expertise in synthesis, place and route, clock tree synthesis, timing closure, physical verification, and signoff.
  • Hands-on experience with Cadence Innovus, Synopsys Fusion Compiler, or comparable implementation platforms.
  • Experience with PrimeTime, Tempus, or equivalent industry-standard signoff tools.
  • Proven ability to work cross-functionally with architects, RTL engineers, EDA vendors, and foundries.

Nice to have

  • Experience with advanced packaging technologies such as 2.5D, 3D, or CoWoS.
  • Experience with IR/EM analysis, thermal optimization, signal integrity, or DFT-aware implementation.

Culture & Benefits

  • Work with an engineering team experienced in semiconductor and AI companies.
  • Help shape first-generation accelerator silicon and future product generations.
  • Medical, dental, and vision coverage.
  • 401(k) and generous paid time off.
  • Meaningful equity participation in addition to base salary.

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