Назад
Company hidden
5 дней назад

Digital IC Design Intern, BS - Summer 2027 (Semiconductor)

30 - 59$
Формат работы
onsite
Тип работы
fulltime
Грейд
trainee
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
Для мэтча и отклика нужен Plus

Мэтч & Сопровод

Для мэтча с этой вакансией нужен Plus

Описание вакансии

Текст:
/
TL;DR
Digital IC Design Intern, BS - Summer 2027 (Semiconductor): Developing and verifying high-performance RTL blocks for Ethernet PHYs, SoCs, cloud, AI, storage, and networking chips with an accent on synthesis, static timing analysis, timing signoff, and power analysis. Focus on debugging design issues, exploring new design flows, and collaborating across architecture, verification, and physical design to deliver robust digital chip solutions.

Location: Santa Clara, California, United States

Salary: $30–$59 per hour

Company

hirify.global develops semiconductor solutions for enterprise, cloud, AI, storage, networking, and carrier data infrastructure.

What you will do

  • Design and implement digital IC and RTL blocks for high-speed connectivity devices and next-generation chips.
  • Verify RTL designs and apply digital design specifications within the ASIC flow.
  • Conduct synthesis, static timing analysis, timing signoff, and power analysis.
  • Debug design issues and ensure functional correctness.
  • Investigate new design techniques, flows, and methodologies to improve design quality and productivity.
  • Collaborate with architecture, design verification, and physical design teams to solve complex chip design problems.

Requirements

  • Currently enrolled in a bachelor's degree program in Electrical Engineering, Computer Engineering, or a related field, with expected graduation between Fall 2027 and Summer 2028.
  • Coursework in circuit design, circuit theory, digital logic design, static timing analysis, computer architecture, Verilog, VLSI, DSP, SoC/ASIC design, or electronics.
  • Programming and scripting proficiency in Python, Perl, or Tcl.
  • Hands-on RTL design experience and understanding of its integration into the ASIC design flow.
  • Experience with Synopsys PrimeTime, Cadence Virtuoso and Spectre X, or Mentor tools.
  • Strong analytical, problem-solving, and communication skills.

Culture & Benefits

  • Paid internship focused on real chip design efforts and next-generation data infrastructure products.
  • Medical, dental, and vision coverage.
  • Mental health resources, paid holidays, perks, and discounts.
  • Additional compensation may be available for PhD intern candidates.
  • Access to export-controlled technology may require eligibility under U.S. export control laws and an export license review.

Hiring process

  • Interviews assess individual experience, thought process, and communication skills in real time.
  • AI tools, transcription applications, automated answer generators, and automated note-taking bots are not permitted during interviews.

Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →