Senior SoC Physical Layout & Full-Chip Integration Engineer (Semiconductor)

Location: Hybrid work model with on-site attendance at assigned hirify.global sites in Hillsboro, Oregon; Phoenix, Arizona; or Austin, Texas, United States.

Annual salary: $122,440–$232,190 USD, depending on work location, skills, experience, and education.

Company

hirify.global Foundry develops semiconductor process technologies, manufacturing capabilities, and silicon platforms for next-generation products.

What you will do

• Lead full-chip floorplanning, physical integration, and tapeout activities for advanced-node silicon development vehicles.
• Develop custom layout methodologies and scalable physical design flows.
• Drive physical verification closure across DRC, LVS, DFM, density, and antenna rules.
• Collaborate with Technology Development, PDK, and EDA teams on manufacturable design solutions and design enablement.
• Analyze advanced-node design rules for FinFET and Gate-All-Around architectures.
• Automate layout creation, checking, and full-chip database manipulation using Tcl, Python, SKILL, or similar tools.

Requirements

• Master's degree in Electrical Engineering, Computer Engineering, or a related field with 4+ years of industry experience, or a PhD in a related field with 1+ years of industry experience.
• Experience in custom, analog, or mixed-signal layout design for advanced technology nodes.
• Knowledge of FEOL layout design rules, transistor-level matching, parasitic layout concepts, and custom silicon structures.
• Experience debugging LVS, DRC, and DFM issues with industry-standard verification engines such as Calibre or ICV.
• Experience using Tcl, Python, or SKILL for layout and database automation.
• Ability to work under the hybrid model at an assigned hirify.global site in the United States.

Nice to have

• Experience with top-level floorplanning, RDL or bump planning, or backside power delivery using PowerVia.
• Experience working with PDK and Technology Development teams on design rules, test structures, or DRC suppression strategies.
• Experience managing physical tapeout schedules, IP tracking matrices, and physical design QA flows.
• Familiarity with Cadence Virtuoso and translating custom databases into full-chip NDM flows.
• Previous semiconductor foundry experience.

Culture & Benefits

• Work with experts across design, process technology, manufacturing, yield engineering, and EDA development.
• Exposure to the full silicon lifecycle, from methodology development through tape-in and silicon validation.
• Competitive compensation with stock bonuses.
• Health, retirement, and vacation benefits.
• Opportunities for technical leadership, career development, and work on advanced semiconductor technologies.