Senior Core Design Verification Engineer (SystemVerilog/UVM)

Location: On-site in Penang, Malaysia

Company

hirify.global develops silicon and platform solutions, including high-performance CPUs and computing platforms.

What you will do

• Perform functional verification of CPU logic against specification requirements.
• Develop and execute IP verification plans, test benches, environments, and coverage strategies for CPU microarchitectures.
• Define and run system simulation models to validate functionality, power, and timing.
• Debug presilicon failures, reproduce issues, and implement corrective measures.
• Collaborate with CPU architects, RTL developers, and physical design teams to meet functional, performance, and power targets.
• Document verification plans, lead technical reviews, maintain verification infrastructure, and contribute to CPU architecture and microarchitecture features.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
• At least 4 years of experience in ASIC or FPGA design verification, preferably involving CPUs or E-Core designs.
• Proficiency in SystemVerilog and UVM.
• Strong scripting and programming skills in Python and C/C++.
• Hands-on experience with industry-standard verification tools and methodologies.
• Effective problem-solving, debugging, communication, and cross-functional collaboration skills.

Nice to have

• Master’s degree with 3 years of relevant experience, or a PhD with no prior professional experience.
• Expertise in platform-level design verification and microprocessor-based systems.

Culture & Benefits

• Full-time experienced-hire position.
• On-site work model with Shift 1 in Malaysia.
• Work within a cross-functional silicon and platform engineering group.
• Employment follows hirify.global’s responsible and ethical hiring practices; recruitment fees are not charged.