7 дней назад
Power Management Design Engineer (RISC-V)
Вакансия из Hirify Global, списка международных tech-компанийДля мэтча и отклика нужен Plus
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Power Management Design Engineer (RISC-V) (CPU/SoC Power Management): Designing clocking, reset, and power-management solutions for configurable RISC-V CPU and SoC IP with an accent on microarchitecture, RTL implementation, and energy-efficient hardware. Focus on developing power states and PMUs, implementing DVFS and power sequencing, verifying RTL, and optimizing physical design for frequency, area, and power targets.
Location: Cambridge, England, United Kingdom. The role requires the right to work in the United Kingdom and authorization to access export-controlled technology or obtain the necessary export licenses.
Company
develops configurable RISC-V CPU and SoC intellectual property for applications including artificial intelligence, machine learning, automotive, data centers, mobile, and consumer devices.
What you will do
- Define power-management requirements with the architecture team.
- Architect, design, and implement clocking, reset, and power-management solutions for RISC-V CPU and SoC IP.
- Develop microarchitectures and maintain clear technical specifications and documentation.
- Perform initial verification and collaborate with design verification engineers on comprehensive test plans.
- Work with physical implementation engineers to optimize frequency, area, and power.
- Collaborate with software engineers to enable and optimize power-management features.
Requirements
- 3+ years of recent industry experience designing CPU and SoC clocking, reset, and power-management logic.
- Experience with high-performance, energy-efficient CPU and SoC designs, including power states, PMU design, clock gating, clock-boundary crossing, retention, power sequencing, DVFS, and Di/dt mitigation.
- Proficiency in RTL design using Verilog, SystemVerilog, or VHDL.
- Experience with RTL quality checks such as lint, CDC, and RDC; SpyGlass experience is a plus.
- Background in CPU or SoC development from architecture through tapeout, plus knowledge of DFT, MBIST, debug, error handling, and power-aware simulation.
- BS/MS degree in EE, CE, CS, or a related technical discipline, or equivalent experience; knowledge of an object-oriented or functional programming language.
Nice to have
- Experience with AMBA protocols including AXI, AHB, APB, P-channel, and Q-channel.
- Experience with Scala/Chisel, Bluespec, or another language or DSL for configurable hardware.
- Knowledge of RISC-V architecture.
- Experience with Git/GitHub, Jira, or Confluence.
Culture & Benefits
- Collaborative engineering culture focused on high-quality hardware design.
- Flexible paid time off.
- Health, vision, and dental benefits.
- 401(k) plan and employee stock option program.
- Equal employment opportunity and an inclusive workplace.
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