Advanced Packaging & Integration Lead (Quantum Computing)

Location: Hybrid in Dublin or Delft

Company

hirify.global develops scalable quantum computing systems based on multi-chip silicon spin-qubit devices.

What you will do

• Define the strategy and architecture for 3D integrated circuits and multi-chip quantum modules.
• Develop packaging solutions using TSVs, fine-pitch micro-bumps, and flip-chip bonding.
• Design packaging architectures and interconnects that remain reliable during thermal cycling to millikelvin temperatures.
• Develop simulations covering signal integrity, power integrity, RF performance, thermal behaviour, and mechanical stress.
• Drive yield improvement, failure analysis, manufacturability, and long-term hardware reliability.
• Coordinate technical activities with external suppliers, OSATs, research partners, and advanced packaging manufacturers.

Requirements

• Master’s or PhD in Electrical Engineering, Materials Science, Physics, Microelectronics, or a related field.
• At least 7 years of experience in 3D integration and advanced packaging, including TSVs, fine-pitch micro-bumps, and flip-chip bonding.
• Experience with 3D-IC layout, planning, simulation platforms, multi-die co-design, TSV floorplanning, and vertical interconnect planning.
• Experience with multiphysics tools such as Ansys HFSS/Q3D or equivalent for signal and power integrity, RF analysis, and cryogenic structural and thermal stress.
• Experience managing technical transfers and working with external semiconductor packaging facilities, OSATs, or research partners.
• Ability to guide technical strategy and collaborate across multidisciplinary engineering teams.

Nice to have

• Experience with cryogenic electronics, semiconductor physics, or silicon spin qubits.
• Knowledge of material behaviour at extreme temperatures, including superconductors and low-loss dielectrics.
• Experience leading or mentoring engineers in a high-tech R&D environment.

Culture & Benefits

• Multidisciplinary collaboration across quantum, semiconductor, materials, and packaging engineering.
• Work on early-stage architecture and co-design for next-generation quantum processors.
• Interaction with external suppliers, OSATs, research partners, and advanced manufacturing facilities.