Mixed Signal IP Integration Engineer (New Grad)

Location: Ottawa, Canada

Salary: CAD 75,100–119,900 per year

Company

hirify.global builds high-speed connectivity infrastructure and networking technologies for the AI era.

What you will do

• Design and integrate custom mixed-signal macros within ASIC flows for next-generation high-baud-rate optical modems.
• Generate Verilog, Library Exchange Format, Liberty timing files, documentation, layout files, and SPICE netlists for chip-level LVS.
• Support macro-level standard-cell interface design, analog-digital timing handoff, and static timing analysis.
• Contribute to digital integrated circuit design using standard-cell libraries.
• Develop design-for-test solutions and models aligned with ASIC test methodologies.

Requirements

• Bachelor’s or master’s degree in electrical or computing engineering.
• Previous internship, co-op, or applied project experience relevant to the role.
• Knowledge of analog design principles, schematic capture, layout, extraction, pre- and post-layout simulation, design rule checking, and layout-versus-schematic verification.
• Strong working knowledge of Cadence custom IC tools.
• Understanding of digital design, including Verilog/RTL, place-and-route, and static timing analysis.
• Experience with Cadence Innovus or Synopsys Integrated Circuit Compiler II.

Nice to have

• Scripting experience in Python and Cadence SKILL.
• Strong oral and written communication skills.
• Confidence working in Windows and Linux environments.

Culture & Benefits

• Collaborative engineering environment focused on innovation, integrity, and professional growth.
• Medical, dental, and vision coverage.
• DCPP participation in Canada with company matching.
• Employee Stock Purchase Program and Employee Assistance Program.
• Paid holidays, sick leave, vacation, and applicable family and other leaves.