R&D Digital Design Engineer (ASIC)

Location: San Jose, California, USA; onsite

Annual base salary: USD 121,900–195,000, plus discretionary annual bonus and equity awards.

Company

hirify.global develops high-performance Ethernet switch silicon and software for hyperscale data centers, cloud providers, enterprise networks, and AI infrastructure.

What you will do

• Develop microarchitecture specifications for complex networking ASIC components.
• Implement efficient RTL for high-performance Ethernet switch silicon.
• Participate in unit verification, timing convergence, ECO implementation, and debug analysis.
• Contribute across the full ASIC development lifecycle from architecture through volume manufacturing.
• Review designs and collaborate across different levels of system abstraction.

Requirements

• Bachelor’s degree in electrical engineering, computer engineering, computer science, or an equivalent field.
• 8 years of experience with a B.S. or 5 years with an M.S. in digital design across multiple networking ASICs.
• 5+ years of experience in Verilog-based RTL design or verification using deep-submicron technologies.
• Familiarity with Ethernet and other networking protocols.
• Analytical problem-solving ability, system-level curiosity, independence, and strong execution skills.

Nice to have

• Extensive experience with Ethernet, TCP/IP, MPLS, tunneling, and other networking protocols.
• Experience with packet-processing architectures, including packet parsing, ACLs, metering, and policing.
• Experience with timing closure, low-power design, power estimation, and clock-domain crossing techniques.
• Experience with Python or Perl scripting.

Culture & Benefits

• Medical, dental, and vision plans.
• 401(k) participation with company matching.
• Employee Stock Purchase Program and Employee Assistance Program.
• Paid holidays, sick leave, vacation time, and applicable family leave.
• Annual bonus, competitive new-hire equity grants, and annual equity awards.