Substrate IC Package Layout Design Engineer (AI)

Location: Taipei, Taiwan; fully on-site

Company

hirify.global is developing AI inference ASICs purpose-built for transformer workloads, targeting substantially higher performance and lower cost and latency than GPU-based systems.

What you will do

• Lead the design of complex IC substrate layouts for high-power AI processors and accelerators.
• Develop large, multilayer substrate packages exceeding 50 mm, with high pin counts and dense routing.
• Design power delivery networks supporting custom silicon solutions above 700 W.
• Develop signal routing for systems operating above 50 GHz while mitigating loss, crosstalk, reflections, and impedance mismatches.
• Optimize CoWoS interposer designs for thermal and electrical performance and collaborate with silicon, SI/PI, packaging, manufacturing, and OSAT teams.
• Perform DRC and LVS verification, maintain design documentation, and provide technical guidance during design reviews.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 10+ years of experience in IC substrate layout design for high-performance processors or accelerators.
• Extensive experience with substrate packages larger than 50 mm, complex high-density layouts, and 700 W+ power delivery designs.
• Expertise in high-speed signaling above 50 GHz and signal integrity mitigation techniques.
• Strong experience with CoWoS interposer design and package-level SI/PI principles.
• Advanced proficiency with Allegro Package Designer, including constraint management, routing, and design verification.

Culture & Benefits

• Fully in-person engineering work in Taipei.
• Close collaboration across engineering, research, silicon, packaging, manufacturing, and system teams.
• Technical staff contribute to both engineering and research as needed.
• Competitive compensation with equity packages.
• Comprehensive insurance coverage and other top-market benefits.