Substrate Layout Design Engineer (AI Infrastructure)

Location: Saratoga, CA, United States

Company

hirify.global is a Silicon Valley hardware startup developing infrastructure solutions that improve AI data center performance, GPU utilization, reliability, and cost efficiency.

What you will do

• Own the end-to-end physical layout of advanced organic substrates and high-density multi-die packages using Siemens Xpedition and Cadence Allegro.
• Perform routing-feasibility studies, optimize die and component placement, bump maps, netlists, layer stack-ups, vias, and escape routing.
• Implement high-speed serial, differential, clock, control, and management routing with impedance, skew, crosstalk, shielding, and return-path constraints.
• Develop power and ground distribution for high-power devices, including plane allocation, current-density management, via arrays, and power-integrity constraints.
• Support package-to-board co-design, fine-pitch interconnects, embedded passives, interface boards, mechanical alignment, and supplier-specific design rules.
• Lead layout reviews, resolve DRC, connectivity, DFM, and manufacturing issues, and prepare release packages and documentation with external suppliers and manufacturers.

Requirements

• 8+ years of hands-on experience in advanced IC package substrate layout, including substantial experience with high-performance organic substrates.
• Experience with multi-die or chiplet-based packages, high I/O counts, fine-pitch bump escape, dense routing, and constrained layer stack-ups.
• Strong hands-on proficiency with Siemens Xpedition for package or substrate layout.
• Experience with package-to-board or complex PCB layout and with releasing layout databases and manufacturing documentation to suppliers.
• Understanding of interactions among die floorplans, substrate layouts, board interfaces, mechanical boundaries, and manufacturing rules.
• Bachelor’s degree in electrical, electronics, packaging, or a related engineering discipline, or equivalent relevant experience.

Nice to have

• Master’s degree in electrical, electronics, packaging, or a related engineering discipline.
• Experience with SerDes, differential pairs, clocks, high-current power and ground structures, and SI/PI constraints.
• Experience with Cadence Allegro Package Designer Plus, advanced substrate materials, buildup processes, microvias, embedded passives, and fine-pitch interconnects.
• Experience taking complex package or board designs from feasibility and floorplanning through supplier review, manufacturing release, and build issue resolution.

Culture & Benefits

• Work on AI infrastructure technology intended to improve data center performance and GPU utilization.
• Collaborate with experienced teams across silicon, packaging, optics, software, systems, manufacturing, and supply chain.
• Work directly with foundries, substrate suppliers, OSATs, PCB fabricators, and contract manufacturers.
• Base salary is determined according to skills, experience, qualifications, work location, market trends, and comparable employee compensation.