Integrated Circuit Designer - Layout (CMOS)

Location: San Jose, California, United States

Company

hirify.global develops rack-scale AI infrastructure and semiconductor connectivity solutions based on CXL, Ethernet, NVLink, PCIe, UALink, and its COSMOS software suite.

What you will do

• Design and develop layouts for advanced-node CMOS integrated circuits.
• Perform floor planning, create building-block layouts, and integrate layouts for PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDR circuits.
• Minimize parasitics and skew while addressing matching, EMIR, antenna rules, DRC, and LVS.
• Manage manufacturing processes, technology yield, and product performance.
• Develop test programs and procedures to verify product performance specifications.
• Advise on semiconductor process technology and maintain and repair semiconductor process equipment.

Requirements

• Bachelor’s degree or higher in electrical engineering.
• 10+ years of experience developing layouts for high-speed analog IC designs in FinFET technology.
• Experience with layout extraction tools and analyzing layout parasitics for high-quality high-speed circuits.
• Knowledge of EMIR and antenna DRC-aware layout practices.
• Ability to collaborate with layout and design engineers across multiple time zones.

Nice to have

• Experience writing SKILL and TCL scripts.

Culture & Benefits

• Competitive salary and 13th-month salary.
• Annual performance bonus and long-term incentive plan.
• Annual health check and insurance for the engineer and family.
• Lunch allowance and company trips.
• Inclusive environment welcoming diverse backgrounds and experiences.