IC Layout Engineer (Semiconductor)

Location: Singapore, Yishun

Company

hirify.global's Library Group is part of the Central Engineering Group and focuses on circuit design for memory, I/O, and standard cells.

What you will do

• Apply layout guidelines, new process rules, and technical requirements for standard-cell, I/O, and memory layouts.
• Plan schedules and layout floor-plans for assigned projects.
• Complete quality layout and verification work within the planned schedule.
• Perform memory layout design and physical verification, including LVS, DRC, ERC, antenna, and electromigration checks.
• Review new technologies and document layout methodologies, flows, and guidelines.
• Lead or train junior engineers and contribute to project management.

Requirements

• 3–4 years of layout engineering experience with strong knowledge of IC layout.
• Experience with Cadence Layout, Cadence Schematic Capture, Virtuoso XL/VXL/EXL, Calibre, and Hercules.
• Experience with submicron CMOS processes, including 16nm, 7nm, 5nm, 3nm, 2nm, or 1.4nm technologies.
• Experience in digital layout for standard cells, memory, and I/O, including floor-planning, hierarchy layout, and chip integration.
• Knowledge of memory layout topology and physical verification in CMOS processes.
• Ability to work independently and collaboratively, communicate effectively, and lead or train junior engineers.

Nice to have

• Analog layout experience.
• Script programming and SKILL programming knowledge.
• Memory compiler experience.

Culture & Benefits

• Work within the Library Group of the Central Engineering Group.
• Collaborate with other members of the library team and remain open to new methodologies and ideas.
• Equal opportunity employment is provided in accordance with applicable law.