Manager, Digital Design (PCIe/CXL)

Location: San Jose, California, United States

Salary: $216,000–$240,000 per year, depending on experience, level, and business need. The role may also be eligible for discretionary bonuses, incentives, and benefits.

Company

hirify.global develops purpose-built connectivity solutions and software for rack-scale AI infrastructure, integrating PCIe, CXL, Ethernet, NVLink, and UALink technologies.

What you will do

• Lead digital chip development from product requirements and architecture through RTL, verification, tape-out, production, and shipment.
• Drive delivery of at least two complex devices with clear milestones, technical decisions, risk tracking, and schedule accountability.
• Translate PCIe, CXL, UAL, and Ethernet requirements into robust, scalable digital implementations.
• Set RTL quality standards, design checklists, review gates, coding practices, and signoff criteria for the digital design lifecycle.
• Resolve performance, power, area, clocking, and integration issues with verification, physical design, DFT, validation, firmware, and operations teams.
• Lead, mentor, and develop a team of 6–8 digital design engineers while communicating technical status, tradeoffs, dependencies, and mitigation plans.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
• Experience with PCIe, CXL, UAL, and Ethernet digital design, including protocol implementation, high-speed connectivity requirements, and physical-layer considerations.
• 3–5 years of engineering management or technical leadership experience in digital IC or ASIC design.
• Ownership of chip design and development from requirements through tape-out and shipment for at least two reasonably complex devices.
• Strong hands-on experience developing front-end RTL and applying design practices that support predictable physical design progress and tape-out quality.
• Ability to lead 6–8 engineers and influence execution across architecture, verification, physical design, DFT, firmware, validation, and operations.

Nice to have

• Expertise in RTL quality methodologies, design reviews, lint, clock-domain and reset-domain considerations, synthesis, timing, and signoff readiness.
• Experience improving design checklists, development flows, quality gates, and cross-functional tape-out processes.
• Experience building design blocks with large physical floorplan sizes.
• Experience balancing performance, power, area, schedule, and risk across large SoC or ASIC programs.
• Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field.

Culture & Benefits

• Work on connectivity products supporting the next generation of AI systems.
• Collaborate with hyperscalers, ecosystem partners, and cross-functional engineering teams.
• Potential eligibility for discretionary bonuses, incentives, and benefits.
• Commitment to diverse ideas, backgrounds, and experiences in the workplace.