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9 дней назад

Senior ASIC Verification Engineer (Networking ASIC)

153 500 - 310 500$
Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Senior ASIC Verification Engineer (Networking ASIC): Building and verifying high-speed networking ASICs and SoC modules with an accent on UVM environments, constraint-driven random testing, functional coverage, and assertion-based verification. Focus on driving block-level and subsystem verification from test planning through coverage closure, debugging complex simulations, and validating networking silicon deliverables.

Location: Hybrid role based in Sunnyvale, California, with an expectation of working in the office 2 days per week

Salary: USD 153,500–310,500 annual base salary in California; variable incentives may also be offered.

Company

A global edge-to-cloud technology company developing networking hardware, software, routers, switches, and high-speed silicon solutions.

What you will do

  • Own block-level or subsystem verification from test planning through comprehensive coverage closure.
  • Develop, enhance, and maintain UVM environments, including agents, sequences, scoreboards, virtual sequences, and register models.
  • Perform constraint-driven random testing and verify functional coverage and SVA assertion goals.
  • Analyze simulation results and debug complex SoC designs using Cadence Xcelium, Synopsys VCS, Mentor Questa, and waveform tools.
  • Collaborate with cross-functional teams to resolve issues and deliver high-quality ASIC and SoC designs.

Requirements

  • 10+ years of experience in ASIC or SoC verification, with ownership from test planning through coverage closure.
  • Strong expertise in SystemVerilog and UVM, including building verification environments from scratch.
  • Deep understanding of randomization, constraints, functional coverage, and assertions using SVA.
  • Hands-on experience with test planning, coverage analysis, and debugging complex SoC designs.
  • Proficiency with Cadence Xcelium, Synopsys VCS, Mentor Questa, and waveform debugging.

Nice to have

  • Experience verifying networking ASICs, packet processing, forwarding engines, fabric interfaces, high-speed interconnects, buffers, or scheduling pipelines.
  • Experience with emulation, hardware acceleration, traffic-model integration, coverage analytics, regression dashboards, or Jenkins-based continuous integration.
  • Knowledge of UPF low-power verification, formal verification, post-silicon bring-up, and debug.

Culture & Benefits

  • Health, financial, and emotional wellbeing benefits for employees and their families.
  • Personal and professional development programs supporting career growth and specialization.
  • Inclusive work environment focused on innovation, teamwork, empowerment, and customer success.
  • Flexible support for managing work and personal needs.

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