Principal / Senior Principal Design Verification Engineer (CXL / PCIe / Ethernet)

Location: San Jose, California, United States

Salary: $185,000–$230,000 annually, depending on experience, level, and business need. Discretionary bonus, incentives, and benefits may also apply.

Company

hirify.global provides rack-scale AI infrastructure through semiconductor-based connectivity solutions integrating CXL, Ethernet, NVLink, PCIe, UALink, and the COSMOS software suite.

What you will do

• Lead verification strategy for complex connectivity IPs and SoC subsystems from architecture through silicon.
• Define reusable verification methodologies, frameworks, best practices, and verification infrastructure across multiple programs.
• Build scalable UVM/SystemVerilog environments with scoreboards, protocol monitors, checkers, assertions, and functional coverage models.
• Drive constrained-random verification, regression automation, coverage closure, sign-off, and continuous integration improvements.
• Lead technical reviews, identify verification risks, and debug RTL, protocol, timing, and integration issues.
• Collaborate with architecture, RTL, firmware, emulation, FPGA, post-silicon validation, and system engineering teams while supporting silicon bring-up and customer issue analysis.

Requirements

• Bachelor’s or master’s degree in electrical, electronics, computer engineering, or a related field.
• At least 10 years of design verification experience for Principal level or 15 years for Senior Principal level.
• Strong expertise in SystemVerilog, UVM, constrained-random verification, coverage-driven methodologies, SVA, functional coverage, and protocol compliance.
• Extensive experience with verification planning, execution, sign-off, RTL and waveform debugging, simulation, and protocol analysis.
• Experience with Synopsys VCS, Cadence Xcelium, Siemens Questa, or comparable industry-standard simulators.
• Experience with CXL, PCIe, Ethernet, AXI, APB, AHB, high-speed SerDes, or memory interfaces; CXL, PCIe, Ethernet, and AI infrastructure expertise are especially relevant.

Nice to have

• Experience with CXL cache, memory, and I/O protocols; PCIe transaction, data link, and physical layers; or Ethernet MAC/PCS/PMA architecture.
• Knowledge of coherency protocols, chiplet-based systems, data center SoCs, AI accelerator connectivity, performance verification, low-power verification, CDC/RDC, formal verification, or Portable Stimulus.
• Python, Perl, Tcl, emulation, FPGA prototyping, customer-facing debug, or post-silicon issue resolution experience.
• Experience delivering large SoCs or complex connectivity IPs through multiple first-pass silicon programs.

Culture & Benefits

• Highly visible technical leadership role with influence over architecture, product quality, and verification standards.
• Mentorship and coaching responsibilities across multiple engineering experience levels.
• Collaboration with geographically distributed teams and cross-functional engineering groups.
• Opportunity to drive automation, reusable verification IP, engineering productivity, and continuous improvement.
• Bonus, incentives, and benefits may be available.