Photonic Layout & Design Flow Engineer (AI)

Location: On-site in Berkeley, California, 5 days per week

Salary: Up to $220,000 annual base salary plus equity

Company

Well-funded photonic computing startup building optical processors and an integrated photonic and electronic IC platform for next-generation AI workloads.

What you will do

• Lead commercial photonic integrated circuit layout and the complete tape-out workflow.
• Establish and improve Cadence-based photonic design flows.
• Integrate photonic components into complete chip-level layouts.
• Work with photonic PDKs and foundry-process requirements.
• Own DRC, LVS, sign-off, and foundry submission.
• Resolve PIC/EIC interfaces, coordinate photonics and electronic IC engineers, and close layout, verification, and integration risks.

Requirements

• Hands-on ownership of a commercial PIC layout and tape-out flow.
• Experience with Cadence Photonics, Cadence Virtuoso, or a closely related commercial environment.
• Experience with PDKs, physical layout, verification, and sign-off.
• Experience taking photonic designs through foundry submission and integrating PIC and EIC designs.
• Ability to build or improve design workflows and guide other designers while remaining hands-on.
• Experience with GlobalFoundries silicon-photonics technology is particularly relevant; transferable commercial-foundry experience may also be considered.

Nice to have

• Experience with Python-based photonics tools.

Culture & Benefits

• Opportunity to establish a foundational design capability for a new photonic computing platform.
• Ownership of a critical part of an integrated photonic and electronic IC system.
• Equity in addition to the base salary.