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3 дня назад

Design Verification Lead (AI Hardware)

Формат работы
onsite
Тип работы
fulltime
Грейд
senior/lead
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Design Verification Lead (AI Hardware) (UVM/SystemVerilog): Building verification methodology, testbench architecture, emulation infrastructure, and validation plans for silicon-photonic AI inference chips with an accent on complex compute ASIC verification and AI-driven verification flows. Focus on leading tapeout closure, gate-level simulation, FPGA-based verification, analog model integration, and coverage-driven testbench development.

Location: Austin, TX or Sunnyvale, CA; full-time onsite position

Company

hirify.global is a startup developing silicon-photonic AI inference chips that use programmable metasurfaces to improve compute performance and energy efficiency.

What you will do

  • Own verification methodology and UVM-based testbench architecture with emphasis on AI-driven flows.
  • Build verification plans spanning module-level simulation, SoC integration, interface checks, top-level I/O, and validation.
  • Specify, evaluate, and integrate third-party verification IP.
  • Own gate-level simulation with SDF-annotated timing for tapeout closure.
  • Extend FPGA-based verification and prototyping harnesses and operate cloud-hosted emulation infrastructure.
  • Build and lead the verification team while partnering with system architecture, RTL design, physical design, DFT, and validation.

Requirements

  • 8–15 years of design verification experience, including leading verification of a GPU-class or complex compute ASIC through tapeout.
  • Deep expertise in UVM and SystemVerilog, including testbench architecture, formal verification, coverage analysis, and CI/CD methodology.
  • Experience with gate-level simulation, SoC integration, independently developed blocks, analog components, and analog model integration.
  • Ability to build verification environments end to end, including emulation infrastructure.
  • Hands-on emulation experience with Palladium or an equivalent platform.
  • Must work onsite in Austin, TX or Sunnyvale, CA.

Nice to have

  • Experience developing analog models with WREAL or equivalent descriptions.
  • FPGA-based verification or prototyping experience.
  • Cadence toolchain experience.
  • Experience using AI tooling to accelerate testbench development and coverage closure.
  • Exposure to silicon photonics or optical component verification.

Culture & Benefits

  • Collaborative engineering environment focused on photonics and AI hardware.
  • 100% coverage of base health plan premiums for employees and dependents, plus HSA contributions.
  • Unlimited PTO.
  • 401(k) matching and stock option opportunities.
  • Dental, vision, life, hospital, critical illness, and accident insurance options.
  • Personalized benefits plans with the option to receive cash for unused selections.

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