Design Verification Engineer (AI)

Location: On-site in Mountain View, California, United States

Salary: $250,000 base plus equity

Company

AI compute startup rebuilding the hardware and software stack around extreme compute density, including silicon, packaging, firmware, compilers, kernels, and infrastructure.

What you will do

• Own end-to-end verification for complex IP, subsystems, or full SoCs.
• Develop verification strategies from block level through SoC and emulation.
• Build UVM testbenches, test plans, coverage models, and reusable verification environments.
• Debug complex functional failures and drive coverage closure.
• Verify CPU subsystems, DMA, NoC, die-to-die interfaces, and multi-SoC systems.
• Partner with architecture, RTL, firmware, and software teams while developing AI-assisted verification flows.

Requirements

• 5+ years of hands-on pre-silicon design-verification experience.
• End-to-end ownership from verification planning through functional closure.
• Strong SystemVerilog and UVM experience.
• Experience with block, subsystem, or full-chip verification.
• Track record of debugging complex IP or SoC designs and interpreting hardware and software specifications.
• Ability to define milestones and deliver against aggressive silicon schedules.

Nice to have

• CPU-subsystem or IP-integration verification experience.
• DMA, NoC, multi-chip, or die-to-die protocol verification experience.
• Palladium, Veloce, or similar emulation experience.
• Formal-verification experience and RISC-V knowledge.
• Post-silicon bring-up and debug experience.

Culture & Benefits

• Senior individual-contributor role with ownership of an entire verification domain.
• Work closely with hardware and software teams across the silicon development lifecycle.
• Contribute to a new AI computing platform from pre-silicon verification through first-silicon bring-up and scale-out.
• Base compensation of $250,000 plus equity.