Physical Design Engineer (AI)

Location: On-site in Mountain View, California, United States

Salary: $250k base plus equity

Company

AI compute startup developing an integrated hardware and software platform focused on extreme compute density.

What you will do

• Own physical design for one or more AI accelerator blocks from synthesis and floorplanning through final sign-off.
• Lead placement, routing, clock-tree synthesis, timing closure, power, area, congestion, and physical verification.
• Develop AI-assisted flows to accelerate physical-design and sign-off timelines.
• Resolve implementation trade-offs with architects and RTL designers.
• Collaborate with EDA vendors, foundries, packaging, and verification teams.
• Deliver complex silicon blocks through tape-out and first silicon.

Requirements

• 8+ years of hands-on physical-design experience.
• Experience with high-performance designs at 7nm or below.
• Full-flow ownership from synthesis and floorplanning through sign-off.
• Strong experience with Cadence Innovus, Synopsys Fusion Compiler, or equivalent tools.
• Hands-on timing sign-off experience with PrimeTime, Tempus, or equivalent.
• Experience collaborating with architecture, RTL, foundry, and EDA teams, including a track record of taking complex silicon through tape-out.

Nice to have

• CoWoS, chiplet, 2.5D, or 3D packaging experience.
• Thermal, IR-drop, electromigration, or signal-integrity sign-off experience.
• DFT-aware physical design experience.
• Experience with AI accelerators, CPUs, GPUs, or other high-performance compute silicon.
• Experience building or improving physical-design automation.

Culture & Benefits

• Work alongside engineers with experience in advanced CPUs, custom AI silicon, and wafer-scale systems.
• Own foundational implementation decisions for a new AI computing platform.
• Work across silicon, packaging, firmware, compilers, kernels, and infrastructure.