обновлено 17 дней назад
Senior ASIC Physical Design Engineer (Space)
170 000 - 250 000$
Вакансия из Hirify Global, списка международных tech-компанийДля мэтча и отклика нужен Plus
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Senior ASIC Physical Design Engineer (ASIC/SoC): Implementing advanced mixed-signal SoCs for next-generation satellite and space systems across the full physical design flow with an accent on timing closure, PPA optimization, and physical sign-off. Focus on designing complex SoC blocks, integrating external physical design deliverables, developing automation, and preparing chips for spaceflight.
Location: United States - Remote
Base salary: $170,000–$250,000 annually, plus equity.
Company
Develops high-power satellite platforms and space systems for commercial and US government missions, with plans to mass-produce satellites for multiple orbits.
What you will do
- Execute the complete physical design flow for complex SoC blocks and top-level integration, from synthesis through GDSII.
- Perform floorplanning, place and route, clock-tree synthesis, static timing analysis, timing closure, and PPA optimization.
- Collaborate with architecture, RTL, verification, DFT, packaging, and front-end teams to ensure clean handoffs and predictable convergence.
- Review external physical design partner deliverables, resolve issues, and maintain schedule alignment.
- Develop scripts, automation, methodologies, tool evaluations, and flow documentation.
- Support physical sign-off, chip integration, ECOs, tapeout preparation, production, and spaceflight.
Requirements
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- 5–10 years of ASIC physical design experience for complex SoCs.
- Hands-on experience with Synopsys ICC2, Fusion Compiler, Cadence Innovus, or equivalent tools.
- Strong knowledge of timing analysis, power optimization, physical verification, hierarchical or flat SoC methodologies, and FinFET technologies.
- Working knowledge of DFT, UPF/CPF power intent, and ECO implementation.
- Must be a US Person under ITAR or otherwise eligible for a federally issued export control license.
Nice to have
- Experience with radiation-hardened or space-qualified ASICs.
- Experience with chip-package co-design, advanced 2.5D/3D packaging, or Gate-All-Around technologies.
- Experience managing physical design service vendors, offshore collaboration, or TSMC sign-off.
- Experience working in geographically distributed cross-functional teams.
Culture & Benefits
- Remote work for this US-based role.
- Paid time off, medical, dental, and vision coverage.
- Life insurance and paid parental leave.
- Equity in the company and additional benefits.
- Collaborative, fast-paced environment focused on developing and flying advanced satellite systems.
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