Senior I/O Chiplet Verification Engineer (UCIe)

Location: Ottawa, Canada preferred; hybrid arrangements may be considered based on the candidate and project needs.

Company

hirify.global supports ASIC, FPGA, verification, and embedded software projects for engineering clients across Canada and internationally.

What you will do

• Build verification plans that map requirements to test scenarios, platforms, coverage goals, and sign-off criteria.
• Develop reusable SystemVerilog/UVM environments, including sequences, agents, scoreboards, reference models, and assertions.
• Integrate vendor VIP and models and verify configured IP, protocol modes, PHY interfaces, and end-to-end connectivity.
• Verify high-speed datapaths, static-switch mappings, data integrity, latency, throughput, reset and recovery behavior.
• Verify CSR access, boot and configuration sequences, sideband management, interrupts, and error handling in collaboration with firmware teams.
• Run simulation, formal, connectivity, low-power, and hardware/software co-simulation checks; automate regressions, triage failures, close coverage, and report verification readiness.

Requirements

• 10+ years of hands-on ASIC verification experience with ownership through tape-out sign-off.
• Strong SystemVerilog and UVM skills, including constrained-random stimulus and reusable testbench architecture.
• Experience writing verification plans, defining coverage, debugging complex failures, and driving functional, assertion, and code-coverage closure.
• Experience with high-speed interfaces, complex SoCs, networking ASICs, or die-to-die interconnects.
• Hands-on experience with VIP integration, reference modeling, scoreboarding, assertion-based verification, multi-clock and reset behavior, and protocol corner cases.
• Strong scripting, regression automation, test/configuration management, independent execution, technical review, and sign-off risk communication skills.

Nice to have

• UCIe, PCIe Gen6/Gen7, Ethernet PCS/FEC, 224G SerDes, or mixed-signal IP verification experience.
• Formal model checking, connectivity verification, power-aware simulation with UPF, FPGA prototyping, or emulation.
• Embedded processor verification, secure boot, AXI/APB, register models, firmware-driven testing, silicon bring-up, or AI-assisted verification workflows.

Culture & Benefits

• Direct technical ownership of connectivity challenges for advanced AI and computing systems.
• Close collaboration with architects, RTL, verification, firmware, physical design, and IP partners.
• Opportunity to shape reusable engineering methods for future chiplet programs.
• Supportive environment focused on sound engineering judgment, collaboration, and sustainable work-life balance.